/* ******************************************************
EOSdigital diaphragm signal converter for old sigma lens
	Ver.0.90(2011.6.22 Wed.)	by ursa_minor
****************************************************** */

module SigmaEF(DCLc, DLCc, DCLl, DLCl, SCL, xin, xout);

input	DCLc;		// Camera->Lens data from Camera
input	DLCl;		// Lens->Camera data from Lens
input	SCL;		// dot clock from camera
output	DLCc;		// Lens->Camera data to Camera
output	DCLl;		// Camera->Lens data to Lens
input	xin;		// xtal input(2.048MHz)
output	xout;		// xtal output
reg		DCLi;
reg		DLCi;
reg		[1:0]c;		// start condition counter
reg		[4:0]count;	// internal counter
reg		[7:0]DCLP;	// Pallarel data
reg		[7:0]DCLP1;
reg		[7:0]DCLP2;
reg		sti;		// stop condition indicator

assign	xout = ~xin;
assign	DCLl = (DCLi == 1'b1) ? 1'b0 : (DCLc ==	1'b1) ? 1'bz : 1'b0;
assign	DLCc = (DLCi == 1'b1) ? 1'bz : (DLCl == 1'b0) ? 1'b0 : 1'bz;

/* start condition is follow */
always @(posedge xout)
	if({SCL, DCLc} == 2'b10) begin
		c	<= (c == 2'b10) ? c : c + 2'b01;
	end else begin
		c	<= (sti == 1'b1) ? c : 2'b00;
	end
	
always @(posedge SCL) begin
		DCLP   <= {DCLP[6:0],DCLc};
		if(c[1] == 1'b1) begin
			case(DCLP1)
				8'b00000000	:	count	<= count + 5'b00001;
				8'b00000111	:	count	<= count + 5'b00001;
				default		:	count	<= 5'b00000;
			endcase
		end else
			count	<= 5'b00000;
end

always @(negedge SCL) begin
	case(count)
		5'b00000	: begin
						DCLP1	<= 8'b00000000;
						DCLP2	<= 8'b00000000;
						DCLi	<= 1'b0;
						DLCi	<= 1'b0;
						sti		<= 1'b1;
					  end
		5'b01000	: begin
						DCLP1	<= DCLP;
						sti		<= (DCLP == 8'b00000111) ? sti : 1'b0;
					  end
		5'b10000	:	DCLi	<= (DCLP[6:0] == 7'b0001001) ? 1'b1 : 1'b0;
		5'b10001	: begin
						DCLP2	<= DCLP;
						DCLi	<= 1'b0;
					  end
/*		5'b10010	:	DLCi	<= DCLP2[7];
		5'b10011	:	DLCi	<= DCLP2[6];
		5'b10100	:	DLCi	<= DCLP2[5];
		5'b10101	:	DLCi	<= DCLP2[4];
		5'b10110	:	DLCi	<= DCLP2[3];
		5'b10111	:	DLCi	<= DCLP2[2];
		5'b11000	:	DLCi	<= DCLP2[1];	*/
		5'b11001	:	DLCi	<= DCLP2[0];
		5'b11010	: begin
						sti		<= 1'b0;
						DLCi	<= 1'b0;
					  end
		default		: begin
						DCLi	<= 1'b0;
						DLCi	<= 1'b0;
					  end
	endcase
end

endmodule